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1 of 28 special features ? 65536 bits electrically programmable read only memory (eprom) communicates with the economy of one signal plus ground ? overdrive mode boosts communication speed to 142kbps ? eprom partitioned into two-hundred fifty-six 256-bit pages for randomly accessing packetized data records ? each memory page can be permanently write- protected to prevent tampering ? device is an ?add only? memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by superseding an old page in favor of a newly programmed page ? reduces control, address, data, power, and programming signals to a single data pin ? 8-bit family code specifies ds1986 communications requirements to reader ? reads over a wide voltage range of 2.8v to 6.0v from -40c to +85c; programs at 11.5v to 12.0v from -40c to +85c ordering information part pin-package DS1986-F3+ f3 microcan ds1986f-5+ f5 microcan +denotes a lead(pb)-free/rohs-compliant package. f3 microcan common i button features ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc t ester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan ? digital identification and information by momentary contact ? chip-based data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to bus master with a single digital signal at 16.3kbps ? standard 16 mm diameter and 1-wire ? protocol ensure compatibility with i button family ? button shape is self-aligning with cup-shaped probes ? durable stainless steel case engraved with registration number withst ands harsh environments ? easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage examples of accessories ds9096p self-stick adhesive pad ds9101 multi-purpose clip ds9093ra mounting lock ring ds9093f snap-in fob ds9092 i button probe f5 microcan ds1986 64kb add-only i button ? www.maxim-ic.com 1-wire and i button are registered trademarks of maxim integrated products, inc. 19-4893; rev 8/09 downloaded from: http:///
ds1986 2 of 28 i button description the ds1986 64kb add-only i button is a rugged read/write data carrier that identifies a nd stores relevant information about the product or person to which it is attached. this information can be accessed with minimal hardware, for example a single port pin of a microcontroller. the ds1986 consists of a factory- lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (0fh) plus 64kb of eprom that is user-pr ogrammable. the power to program and read the ds1986 is derived entirely from the 1-wire communicat ion line. data is transferred serially via the 1-wire protocol that requires onl y a single data lead and a ground return. the entire device can be programmed and then write-protected if desired. a lternatively, the part may be programmed multiple times with new data being appended to, but not overwriting, existing data with each subsequent programming of the device. note: individual bits can be changed only from a logi cal 1 to a logical 0, never from a logical 0 to a logica l 1. a provision is also included for indicating that a certain page or pages of data are no longer valid an d have been replaced with new or updated data that is now residing at an alternate page address. this page address redire ction allows software to patch data and enhance the flexibility of the device as a standa lone database. the 48-bit serial numb er that is factory-lasered into each ds1986 provides a guaranteed unique identity that allows for absolute traceability. the durable microcan package is highly resistant to harsh environments such as di rt, moisture, and shock. its compact button-shaped profile is self-aligning with cup-shaped receptacles, allowing the ds1986 to be used easily by human operators or automatic equipment. accesso ries permit the ds1986 to be mounted on printed circuit boards, plastic key fobs, photo-id badges, id bracelets, a nd many other objects. applications include work-in-progress tracking, elec tronic travelers, access control, storage of calibration constants, and debit tokens. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds1986. the ds1986 has three main data com ponents: 1) 64-bit lasered rom, 2) 65536 bits eprom data memory, and 3) 2816 b its eprom status memory. the de vice derives its power for read operations entirely from the 1-wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and conti nues to operate off of this ?parasite? power source during the low times of the 1-wire line until it returns high to replenish the para site (capacitor) supply. during programming, 1-wire communication occurs at normal voltage levels and then is pulsed momentarily to the programming voltage to cause th e selected eprom bits to be programmed. the 1- wire line must be able to provide 12 volts and 10 milliamperes to adequately program the eprom portions of the part. whenever programming voltage s are present on the 1-wire line a special high voltage detect circuit within the ds 1986 generates an internal logic sign al to indicate this condition. the hierarchical structure of the 1-wire protocol is shown in figure 2. th e bus master must first provide one of the six rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom, 5) overdrive-skip rom, or 6) overdrive-match ro m. upon completion of an overdrive rom command byte executed at regular speed, the device will en ter the overdrive mode where all subsequent communication occurs at a higher speed. these commands operate on the 64-bit lasered rom portion of each device and can singulate a specific device if many are present on the 1-wire line as well as indicate to the bus master how many and what types of devices are present. the protocol required for these rom function commands is described in figure 8. after a rom function co mmand is successfully executed, the memory functions that operate on the eprom por tions of the ds1986 become accessible and the bus master may issue any one of the five memory f unction commands specific to the ds1986 to read or program the various data fields. the protocol for these memory function commands is described in figure 5. all data is read and writ ten least significant bit first. downloaded from: http:///
ds1986 3 of 28 64-bit lasered rom each ds1986 contains a unique rom code that is 64 b its long. the first eight bits are a 1-wire family code. the next 48 bits are a unique serial number. th e last eight bits are a crc of the first 56 bits. (see figure 3.) the 64-bit rom and rom function control section allow the ds1986 to operate as a 1-wire device and follow the 1-wire protocol detailed in the section ?1-wire bus system?. the memory functions required to read and pr ogram the eprom sections of the ds1986 are not accessible until the rom function protocol has been sati sfied. this protocol is described in the rom functions flow chart (figure 8). the 1-wire bus master must first provi de one of six rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom, 5) overdrive-sk ip rom, or 6) overdrive-match rom. after a rom function sequence has been successf ully executed, the bus ma ster may then provide any one of the memory function commands specific to the ds1986 (figure 5). the 1-wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas semiconductor 1-wire cy clic redundancy check is available in the book of ds19xx i button standards. the shift register acting as the crc accumulator is initialized to zero. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the eighth bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc valu e. shifting in the eight bits of crc should return the shift register to all zeros. downloaded from: http:///
ds1986 4 of 28 ds1986 block diagram figure 1 downloaded from: http:///
ds1986 5 of 28 hierarchical structure for 1-wire protocol figure 2 1-wire bus other devices 64-bit lasered rom figure 3 8- bit crc code 48- bit serial number 8- bit family code (0fh) msb lsb msb lsb msb lsb 65536-bits eprom the memory map in figure 4 shows the 65536-bit epro m section of the ds1986 th at is configured as 256 pages of 32 bytes each. the 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. data is first written to the scratchpad and then ve rified by reading a 16-bit crc from the ds1986 that confirms proper receipt of th e data and address. if the buffer contents are correct, a programming voltage should be applied and th e byte of data will be written into the selected address in memory. this process ensures data inte grity when programming the memory. the details for reading and programming the 65536-bit eprom portio n of the ds1986 are given in the memory function commands section. bus master ds1986 command available data field level: commands: affected: r e a d r o m 6 4 - b i t r o m m a t c h r o m 6 4 - b i t r o m s e a r c h r o m 6 4 - b i t r o m s k i p r o m n / a overdrive skip rom n/a overdrive match rom 64-bit rom w r i t e m e m o r y 6 4 k b i t e p r o m w r i t e s t a t u s e p r o m s t a t u s b y t e s read memory 64k bit eprom read status eprom status bytes extended read data 64k bit eprom 1-wire rom function commands (see figure 9) ds1986 - specific memory function commands (see figure 6) downloaded from: http:///
ds1986 6 of 28 eprom status bytes in addition to the 65536 bits of data memory the ds1986 provides 2816 bits of status memory accessible with separate commands. the eprom status bytes can be read or programmed to indicate various condi tions to the software interrogating the ds1986. the first 32 bytes of the eprom status memory (addresses 000 to 01fh) contain the write protect page bits that inhibit programming of th e corresponding page in the 65536-bit main memory area if the approp riate write protection bit is pr ogrammed. once a bit has been programmed in the write protect page section of the status memory, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be read. the next 32 bytes of the eprom status memory (addr esses 020 to 03fh) contain the write protect bits that inhibit altering the page address redirection byte corresponding to each page in the 65536-bit main memory area. the following 32 bytes within the eprom status memo ry (addresses 040 to 05fh) are reserved for use by the i button operating software tmex. their purpose is to indicate which memory pages are already in use. originally, all of these bits are unprogrammed, indicating that th e device does not store any data. as soon as data is written to any page of the device under control of tmex, the bit inside this bitmap corresponding to that page will be programmed to 0, marking this pa ge as used. these b its are application flags only and have no impact on th e internal logic of the ds1986. the next 256 bytes of the eprom status memory (a ddresses 100h to 1ffh) contain the page address redirection bytes that indi cate if one or more of th e pages of data in the 65536-bit eprom section have been invalidated by software and redi rected to the page address contai ned in the appropriate redirection byte. the hardware of the ds1986 makes no decisions based on the contents of the page address redirection bytes. since with epro m technology bits can only be change d from a logical 1 to a logical 0 by programming, it is not possible to simply rewrit e a page if the data requires changing or updating. but with space permitting, an entire page of data can be redirected to another page within the ds1986. under tmex a page is redirected by writing the one?s complement of the new page address into the page address redirection byte that corresponds to the orig inal (replaced) page. this architecture allows the user?s software to make a ?data patch? to the eprom by indicating that a particul ar page or pages should be replaced with those indicat ed in the page address redirection byte s. to leave an authentic audit trail of data patches, it is recommended to also program the write protect bit of the page address redirection byte, after the page redirection is programmed. without this protection, it is still possible to modify the page address redirection byte, ma king it point to a different memo ry page than the true one. if a page address redirection byte has a ffh value, th e data in the main memory that corresponds to that page is valid. if a page address redirection byte ha s some other hex value than ffh, the data in the page corresponding to that redirection byte is invalid. according to the tm ex definitions the valid data can now be found at the one?s complement of the page address indicated by the hex value stored in the associated page address redirect ion byte. a value of fdh in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. the status memory is programmed similarly to the data memory. details for reading and programming the eprom status memory portion of the ds1986 are given in the memory function commands section. the status memory address range of the ds1986 exte nds from 000 to 1ffh. the memory locations 60h to 0ffh and 200h and higher are physically not impl emented. reading these locations will usually result in ffh bytes. attempts to write to these locations will be ignored. downloaded from: http:///
ds1986 7 of 28 ds1986 memory map figure 4 redirection bytes bit map of used pages write-protect bits redirection bytes write-protect bits data memory status memory map 8 bytes write-protect bits data memory write-protect bits of redirection bytes bit map of used pages reserved for future extensions redirection bytes memory function commands the ?memory function flow chart? (figure 5) de scribes the protocols ne cessary for accessing the various data fields within the ds1986. the memory function control section, 8-bit scratchpad, and the program voltage detect circuit combine to interpre t the commands issued by the bus master and create the correct control signals within th e device. a three-byte protocol is issued by the bus master. it is comprised of a command byte to determine the type of operation and two addre ss bytes to determine the specific starting byte location within a data field. the command byte indicates if th e device is to be read or written. writing data involves not only issuing the correct comma nd sequence but also providing a 12- 8-bit scratchpad 32-byte final storage eprom 32-byte final storage eprom 32-byte final storage eprom 0000h 0020h 0040h 1fe0h 64k bit eprom 325 bytes status memory page 0 page 1 page 255 44 pages of 8 bytes each 000h 01fh 020h 03fh 040h 05fh 060h offh 100h ? ? ? ? 1ffh bit 0 of address 000h=write- protect of page 0, etc. address 100h=page address redirection byte for page 0, etc. starting address downloaded from: http:///
ds1986 8 of 28 volt programming voltage at the appropr iate times. to execute a write se quence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. write sequences always occur a byte at a time. to execute a read sequence, the star ting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. al l bits transferred to the ds1986 a nd received back by the bus master are sent least significant bit first. read memory [f0h] the read memory command is used to read data fr om the 65536-bits eprom data field. the bus master follows the command byte with a two-byte addre ss (ta1=(t7:t0), ta2=(t15: t8)) that indicates a starting byte location within the data field. with ev ery subsequent read data time slot the bus master receives data from the ds1986 starting at the initial address and continuing until the end of the 65536-bits data field is reached or until a reset pulse is issue d. if reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and the ds1986 will respond with a 16-bit crc of the command, address bytes and all data bytes r ead from the initial starting byte through the last byte of memory. this crc is the result of clearing the crc generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to th e last byte of the eprom data memory. after the crc is received by the bus master, any subsequent read time slots will a ppear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse pr ior to reaching the end of memory will not have the 16-bit crc available. typically a 16-bit crc would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see book of ds19xx i button standards, chapter 7 for the recommended file structure to be used with the 1- wire environment.) if crc values are imbedded within the data, a reset pulse may be issued at the end of memory space during a read memory command. read status [aah] the read status command is used to read data fr om the eprom status data field. the bus master follows the command byte with a two-byte addre ss (ta1=(t7:t0), ta2=(t15: t8)) that indicates a starting byte location within the data field. with ev ery subsequent read data time slot the bus master receives data from the ds1986 star ting at the supplied address and c ontinuing until the end of an eight- byte page of the eprom status data field is reache d. at that point the bus ma ster will receive a 16-bit crc of the command byte, address bytes and status data bytes. this crc is computed by the ds1986 and read back by the bus master to check if the command word, st arting address and data were received correctly. if the crc read by the bus master is inco rrect, a reset pulse must be issued and the entire sequence must be repeated. note that the initial pass through the read status flow chart will generate a 16-bit crc value that is the result of clearing the crc generator and then shif ting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed me mory location and continuing through to the last byte of the addressed eprom status data pa ge. the last byte of a status data page always has an ending address of xx7 or xxfh. s ubsequent passes through the read st atus flow chart will generate a 16-bit crc that is the result of clear ing the crc generator and then shifti ng in the new data bytes starting at the first byte of the next page of the eprom status data field. this feature is provided since the eprom status information may change over time making it impossible to program the data once and include an accompanyi ng crc that will always be valid. therefore, the read status command supplies a 16-bit crc that is ba sed on and always is consistent with the current data stored in the epro m status data field. downloaded from: http:///
ds1986 9 of 28 memory function flow chart figure 5 1), 2) see next page downloaded from: http:///
ds1986 10 of 28 memory function flow chart figure 5 (cont.) 1) to be transmitted or received at overdrive speed if od=1; 2) reset pulse to be transmitted at overdrive speed if od=1; reset pulse to be transmitted at regular speed if od=0 or if the ds 1986 is to be reset from overdrive speed to regular speed downloaded from: http:///
ds1986 11 of 28 memory function flow chart figure 5 (cont.) 1), 2) see previous page downloaded from: http:///
ds1986 12 of 28 after the 16-bit crc of the last eprom status data pa ge is read, the bus master will receive logical 1s from the ds1986 until a reset pulse is issued. the r ead status command sequence can be ended at any point by issuing a reset pulse. extended read memory [a5h] the extended read memory command supports page redirection when reading data from the 65536-bit eprom data field. one major difference between the extended read memory and the basic read memory command is that the bus master receives the redirection byte first before investing time in reading data from the addressed memory location. this allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to terminate and restart the reading process at the redirected page address. a non-redirected page is identified by a redirection byte with a value of ffh (see description of epro m status bytes). if the redirection byte is different than this, the master has to complement it to obtain the new page number. multiplying the page number by 32 (20h) results in the new address the master has to send to the ds1986 to read the updated data replacing the old data. there is no logical limitation in the nu mber of redirections of any page . the only limit is the number of available memory pages within the ds1986. in addition to pa ge redirection, the extended read memory command also supports ?bit-oriented? applications where the user cannot st ore a 16-bit crc with the data itself . with bit-oriented applications the eprom information may change over time with in a page boundary making it impossible to include an accompanying crc that will always be valid. therefore, the extended read memory command concludes each page with the ds1986 generating and supplying a 16-bit crc that is based on and therefore always consistent with th e current data stored in each page of the 65536-bit eprom data field. after having sent the command code of the extende d read memory command, the bus master follows the command byte with a two-byte a ddress (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. by se nding eight read data time slots, the master receives the redirection byte associated with the page given by the starting address. with the next sixteen read data time slots, the bus master receives a 16-b it crc of the command byte, address bytes and the redirection byte. this crc is computed by the ds1986 and read back by the bus master to check if the command wor d, starting address and redirection byte were received correctly. if the crc read by the bus master is incorrect, a reset pulse must be i ssued and the entir e sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the ds1986 starting at the initial address and continuing until the end of a 32-byte page is reached. at that point the bus master will send sixteen additi onal read time slots and receive a 16- bit crc that is the result of shifti ng into the crc generator all of the data bytes fr om the initial starting byte to the last byte of the current page. with the next 24 read data time slots the master will receive the redirection byte of the next page followed by a 16-bit crc of the redirection byte. after this, data is again read from the 65536-bit eprom data field starting at the be ginning of the new page. this sequen ce will continue until the final page and its accompanying crc are read by the bus master. the extended read memory command provides a 16-bit crc at two locations within the transaction flow chart: 1) after the redirection byte and 2) at the end of each memory page. the crc at the end of the memory page is always the result of cleari ng the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. with the initial pass through the extended read memory flow chart the 16-bit crc value is the result of downloaded from: http:///
ds1986 13 of 28 shifting the command byte into the cleared crc genera tor, followed by the tw o address bytes and the redirection byte. subsequent passes through the exte nded read memory flow chart will generate a 16- bit crc that is the result of clearing the crc generator and then sh ifting in the redirection byte only. after the 16-bit crc of the last page is read, the bus master will receive logical 1s from the ds1986 until a reset pulse is issued. the extended read memory command sequence can be exited at any point by issuing a reset pulse. writing eprom memory the ds1986 has two independent eprom memory fi elds, data memory and status memory. the function flow for writing either field is almost id entical. after the appropria te write command has been issued, the bus master will send a two-byte starting address (ta1=(t7 :t0), ta2=(t15:t8)) and a byte of data (d7:d0). a 16-bit crc of the command byte, address bytes, and data byte is computed by the ds1986 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the en tire sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 ? s) is issued by the bus master. prior to programming, the entire eprom memory field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the eprom memory is prog rammed to a logical 0 after the programming pulse has been applied. after the 480 ? s programming pulse is applied a nd the data line returns to the idle level (5 volts), the bus master issues eight read time slots to verify that the appropriate bits have been programmed. the ds1986 responds with the data from the selected eprom address sent least significant bit first. this byte contains the bitwise logical and of all data ever written to th is address. if the eprom byte contains 1s in bit positions where the byte issued by the master containe d 0s, a reset pulse should be issued and the current byte address should be programmed again. if the ds 1986 eprom byte contains 0s in the same bit positions as the data byte, the programming was su ccessful and the ds1986 will automatically increment its address counter to select the next byte in th e eprom memory field. the new two-byte address will also be loaded into the 16-bit crc ge nerator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds1986 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the current address and the result is a 16-bit crc of the new data byte and the new address. after supplying the data byte, the bus master will read this 16-bit crc from the ds1986 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is inco rrect, a reset pulse must be issued and the write sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write flow chart will generate an 16-bit crc value that is the result of shifting the command byte into the crc generator, followed by the tw o address bytes, and finally the data byte. subsequent passes thr ough the write flow char t due to the ds1986 auto matically incrementing its address counter will generate a 16-bit crc that is the result of loading (not shifting) the new (incremented) address into the crc generator an d then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds1986) is made entirely by the bus master, since th e ds1986 will not be able to determin e if the 16-bit crc calculated by downloaded from: http:///
ds1986 14 of 28 the bus master agrees with the 16-bit crc calculate d by the ds1986. if an incorrect crc is ignored and a program pulse is applied by th e bus master, incorrect programm ing could occur within the ds1986. also note that the ds1986 will always increment its internal address coun ter after the recei pt of the eight read time slots used to confirm th e programming of the selected eprom byte. the decision to continue is again made entirely by the bus master. therefore if the eprom data byte does not match the supplied data byte but the master continues with the write command, incorrect programming could occur within the ds1986. the write command sequence can be e nded at any point by issuing a reset pulse. write memory [0fh]/speed write memory [f3h] the write memory command is used to program th e 65536-bit eprom data field. the details of the functional flow chart are described in the section ?writing eprom memory?. the data memory address range is 0000h to 1fffh. if the bus master sends a starting address higher than this, the three most significant address bits are set to zeros by the internal circuitry of the chip. this will result in a mismatch between the crc calculate d by the ds1986 and the crc calculated by the bus master, indicating an error condition. to save time when writing more than one consecutive byte of the ds1986?s data memory it is possible to omit reading the 16-bit crc which allows verification of data and address before the data is copied to the eprom memory. at regular speed this saves 16 time slots or 976 ? s for every byte to be programmed. this speed programming mode is accessed with the command code f3h instead of 0fh. it follows basically the same flow chart as the write memory command, but skips sending the crc immediately preceding the program pulse. this command should only be used if the electric al contact between bus master and the ds1986 is firm since a poor contact may result in corrupted data inside the eprom memory. write status [55h]/ spee d write status [f5h] the write status command is used to program the 2816-bit eprom status memory field. the details of the functional flow chart are described in the section ?writing eprom memory?. the status memory address range is 0000h to 01ffh. attempts to write to the not implemented status memory locations will be ignored. if the bus master sends a starting address higher than 1fffh, the three most significant address bits are set to zeros by the in ternal circuitry of the chip. this will result in a mismatch between the crc calculated by the ds 1986 and the crc calculated by the bus master, indicating an error condition. to save time when writing more than one consecutive byte of the ds1986?s stat us memory it is possible to omit reading the 16-bit crc which allo ws verification of data and addre ss before the data is copied to the eprom memory. at regular speed this saves 16 time slots or 976 ? s for every byte to be programmed. this speed-programming mode is accesse d with the command code f5h instead of 55h. it follows basically the same flow chart as the write status command, but skips sending the crc immediately preceding the program pul se. this command should only be us ed if the electrical contact between bus master and the ds1986 is firm since a poo r contact may result in co rrupted data inside the eprom status memory. downloaded from: http:///
ds1986 15 of 28 1-wire bus system the 1-wire bus is a system that has a single bus ma ster and one or more slav es. in all instances, the ds1986 is a slave device. the bus ma ster is typically a microcontrolle r. the discussion of this bus system is broken down into three topics: hardware configuration, tr ansaction sequence, and 1-wire signaling (signal type and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the fall ing edge of sync pulses from the bus master. for a more detailed protocol de scription, refer to chapte r 4 of the book of ds19xx i button standards. hardware configuration the 1-wire bus has only a si ngle line by definition; it is important that each devi ce on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open drain connection or 3- state outputs. the ds1986 is an open dr ain part with an internal circuit equivalent to that shown in figure 6. the bus master can be the same equivalent ci rcuit. if a bidirectional pin is not available, separa te output and input pins can be tied together. the bus master requires a pull-up resi stor at the master end of the bu s, with the bus master circuit equivalent to the one shown in figures 7a and 7b. the value of the pull-up resistor should be approximately 5k ?? for short line lengths. a multidrop bus consists of a 1-wire bus with multiple slaves attached. at regular speed the 1-wire bus has a maximum data rate of 16.3kbps. the speed can be boosted to 142kbps by activating the overdrive mode. if the bus master is also required to pe rform programming of the ep rom portions of the ds1986, a programming supply capable of deliveri ng up to 10 milliamps at 12 volts for 480 ? s is required. the idle state for the 1-wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 ? s (overdrive speed) or more than 120 ? s (regular speed), one or more of the devices on the bus may be reset. transaction sequence the sequence for accessing the ds1986 via the 1-wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus mast er followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus ma ster know that the ds1986 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. downloaded from: http:///
ds1986 16 of 28 rom function commands once the bus master has detected a presence, it can issue one of the six ro m function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 8): read rom [33h] this command allows the bus master to read the ds1986?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can be used onl y if there is a single ds1986 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the resultant family code and 48-bit serial number will usually result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds1986 on a multidrop bus. only the ds1986 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit rom c ode. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pull-downs will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search ro m command allows the bus master to use a process of elimination to identify the 64 -bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple 3-step routine: read a bit, read the comp lement of the bit, then write the desired value of that bit. the bus master performs this simple, 3-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be iden tified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discu ssion of a rom search, including an actual example. downloaded from: http:///
ds1986 17 of 28 ds1986 equivalent circuit figure 6 bus master circuit figure 7 vp0300l or vp0106n3 or bss110 capacitor added to reduce coupling on data line due to programming signal switching to data connection of ds1986 data 5 ? a typ downloaded from: http:///
ds1986 18 of 28 rom functions flow chart figure 8 1) to be transmitted or received at overdrive speed if od=1 2) the presence pulse wi ll be short if od=1 downloaded from: http:///
ds1986 19 of 28 rom functions flow chart figure 8 (cont.) to figure 8 first part from figure 8 first part 3) always to be transmitted at overdrive speed. downloaded from: http:///
ds1986 20 of 28 overdrive skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64- bit rom code. unlike the normal skip rom command the overdrive skip rom sets the ds1986 in the overdrive mode (od=1). all communication following this command has to occur at overdrive speed until a reset pulse of minimum 480 ? s duration resets all devices on the bus to regular speed (od=0). when issued on a multidrop bus this command will se t all overdrive-capable devices into overdrive mode. to subsequently address a specific overdrive- capable device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this will shorten the time for the search process. if more than one slav e supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read co mmand, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pull-downs will produce a wired-and result). overdrive match rom [69h] the overdrive match rom command, followed by a 64-bit rom sequence transmitted at overdrive speed, allows the bus master to address a specifi c ds1986 on a multidrop bus and to simultaneously set it in overdrive mode. only the ds1986 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive skip or match command will remain in overdrive m ode. all other slaves that do not match the 64-bit rom sequence or do not support overdriv e will return to or remain at regular sp eed and wait for a reset pulse of minimum 480 ? s duration. the overdrive match rom command can be used with a single or multiple devices on the bus. 1-wire signaling the ds1986 requires strict protocols to ensure data integrity. the prot ocol consists of five types of signaling on one line: reset sequen ce with reset pulse and presence pu lse, write 0, write 1, read data and program pulse. all these signals except presen ce pulse are initiated by th e bus master. the ds1986 can communicate at two different speeds, regular speed and overdrive speed. if not explicitly set into the overdrive mode, the ds1986 will communicate at regu lar speed. while in overdrive mode the fast timing applies to all communication-related waveforms. the initialization sequence required to begin any communication with the ds1986 is shown in figure 9. a reset pulse followed by a presence pulse indicates the ds1986 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 ? s at regular speed, 48 ? s at overdrive speed). the bus master then releases the line and goe s into receive mode (rx). the 1-wire bus is pulled to a high state via the pull-up resi stor. after detecting the rising edge on the data pin, the ds1986 waits (t pdh , 15-60 ? s at regular speed, 2-6 ? s at overdrive speed) and then transmits the presence pulse (t pdl , 60-240 ? s at regular speed, 8-24 ? s at overdrive speed). a reset pulse of 480 ? s or longer will exit the overdrive mode returning the device to regular speed. if the ds1986 is in overdrive mode and the reset pulse is no longer than 80 ? s the device will remain in overdrive mode. downloaded from: http:///
ds1986 21 of 28 read/write time slots the definitions of write and read time slots are illu strated in figure 10. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds1986 to the master by triggering a delay circuit in th e ds1986. during write time slots, the delay circuit determines when the ds1986 will sample the data line. for a read data time sl ot, if a ?0? is to be tr ansmitted, the delay circuit determines how long the ds1986 will hold the data line low overriding the 1 generated by the master. if the data bit is a ?1?, the i button will leave the read data time slot unchanged. program pulse to copy data from the 8-bit scratchpad to the ep rom data or status memo ry, a program pulse of 12 volts is applied to the data line after the bus master ha s confirmed that the crc for the current byte is correct. during programming, the bus master controls th e transition from a state where the data line is idling high via the pull-up resistor to a state where the data line is ac tively driven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the ds1986. this programming voltage (figure 11) should be applied for 480 ? s, after which the bus master returns the data line to an idle high state controlled by the pull-up resi stor. note that due to the high voltage programming requirements for any 1-wire eprom device, it is not possible to multi-drop non-eprom based 1-wire devices with the ds1986 during programming. an internal diode with in the non-eprom based 1-wire devices will attempt to clamp the data line at approximately 8 volts and could potentiall y damage these devices. initialization procedure r eset and prese nce pulses figure 9 regular speed overdrive speed 480 ? s ? t rstl < ? ? 4 8 ? s ? t rstl < 80 ? s 480 ? s ? t rsth < ? (includes recovery time) 48 ? s ? t rsth < ? 1 5 ? s ? t pdh < 60 ? s 2 ? s ? t pdh < 6 ? s 6 0 ? s ? t pdl < 240 ? s 8 ? s ? t pdl < 24 ? s ? in order not to mask interrupt signali ng by other devices on the 1-wire bus, t rstl + t r should always be less than 960 ? s. resistor master ds1986 downloaded from: http:///
ds1986 22 of 28 read/write timing diagram figure 10 write-one time slot regular speed overdrive speed 6 0 ? s ? t slot < 120 ? s 6 ? s ? t slot < 16 ? s 1 ? s ? t low1 < 15 ? s 1 ? s ? t low1 < 2 ? s 1 ? s ? t rec < ? 1 ? s ? t rec < ? write-zero time slot regular speed overdrive speed 60 ? s ? t low0 < t slot <120 ? s 6 ? s ? t low0 < t slot <16 ? s 1 ? s ? t rec < ? 1 ? s ? t rec < ? resistor master ds1986 downloaded from: http:///
ds1986 23 of 28 read/write timing diagram figure 10 (cont.) read-data time slot regular speed overdrive speed 60 ? s ? t slot < 120 ? s 6 ? s ? t slot < 16 ? s 1 ? s ? t lowr < 15 ? s 1 ? s ? t lowr < 2 ? s 0 ? t release < 45 ? s 0 ? t release < 4 ? s 1 ? s ? t rec < ? 1 ? s ? t rec < ? t rdv = 15 ? s t rdv = 2 ? s t su < 1 ? s t su < 1 ? s program pulse timing diagram figure 11 crc generation with the ds1986 there are two different types of crcs (cyclic redundancy checks). one crc is an 8- bit type and is stored in the most significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of th e 64-bit rom and compare it to the value stored within the ds1986 to determine if the rom data has been received error-f ree by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8-bit crc is received in th e true (non-inverted) form when reading the rom of the ds1986. it is computed on ce at the factory and lasered into the rom. resistor master ds1986 t dp t pp t dp line type legend: bus master active high (12v @ 10 ma) resistor pull-up downloaded from: http:///
ds1986 24 of 28 the other crc is a 16-bit type, generated according to the standardized crc16-polynomial function x 16 + x 15 + x 2 + 1. this crc is used to safeguard user-defin ed eprom data when reading data memory or status memory. it is the same type of crc as is used with nvram based i buttons to safeguard data packets of the i button file structure. in contrast to the 8- bit crc, the 16-bit crc is always returned in the complemented (inverted) form. a crc-generator in side the ds1986 chip (figure 12) will calculate a new 16-bit crc at every situation shown in the command flow chart of figure 5. the ds1986 provides this crc-value to the bus master to validate the transfer of command, address, and data to and from the bus master. when reading th e data memory of the ds1986 with the read memory command, the 16-bit crc is only transmitted as the end of the memory is reached. this crc is generated by clearing the crc gene rator, shifting in the command, low address, high address and every data byte starting at the first addr essed memory location and continuing until the end of the implemented data memory is reached. when reading the status memory with the read st atus command, the 16-bit crc is transmitted when the end of each 8-byte page of the status memory is reached. at the initia l pass through the read status flow chart the 16-bit crc will be generated by clearing th e crc generator, shifting in the command byte, low address, high address and the data bytes beginning at the first addressed memory location and continuing until the last byte of the addressed eprom status da ta page is reached. subsequent passes through the read status flow chart will genera te a 16-bit crc that is the resu lt of clearing the crc generator and then shifting in the new data bytes starting at the fi rst byte of the next page of the eprom status data field and continuing until the last byte of the page is reached. when reading the data memory of the ds1986 with the extended read memory command, there are two situations where a 16-bit crc is transmitted. one 16-b it crc follows each redirection byte, another 16- bit crc is received after the last byte of a memory data page is read. the crc at the end of the memory page is always the result of clear ing the crc generator and shifting in th e data bytes beginning at the first addressed memory location of the eprom data page un til the last byte of this page. with the initial pass through the extended read memory flow chart the 16-bit crc value is the re sult of shifting the command byte into the cleared crc generator, follo wed by the two address bytes and the redirection byte. subsequent passes through the extended read me mory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only. when writing to the ds1986 (either data memory or st atus memory), the bus master receives a 16-bit crc to verify the correctness of the data transfer before applying the programming pulse. with the initial pass through the write memory/status flow chart the 16-bit crc will be generated by clearing the crc- generator, shifting in the comma nd, address low, address high and the data byte. subsequent passes through the write memory/status flow chart due to the ds1986 automatically incrementing its address counter will generate an 16-bit crc th at is the result of loading (not shifting) the new (incremented) address into the crc generator and th en shifting in the new data byte. the comparison of crc values and decision to continue with an operation are de termined entirely by the bus master. there is no circuitry on the ds1986 that prevents a command sequence from proceeding if the crc stored in or calculated by the ds1986 does not match the value generate d by the bus master. for more details on generating crc values including example implementations in both hardware and software, see the book of ds19xx i button standards. downloaded from: http:///
ds1986 25 of 28 crcC16 hardware descript ion and polynomial figure 12 polynomial = x 16 + x 15 + x 2 + 1 downloaded from: http:///
ds1986 26 of 28 absolute maxi mum ratings* voltage on any pin relative to ground -0.5v to +12.0v operating temperature -40c to +85c storage temperature -55c to +125c ? this is a stress rating only and functional operati on of the device at these or any other conditions outside those indicated in the ope ration sections of th is specification is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1,6 logic 0 v il -0.3 +0.8 v 1,10 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1,2 input load current i l 5 ? a 3 operating charge q op 30 nc 7,8 programming voltage @ 10 ma v pp 11.5 12.0 v capacitance (t a = 25c) parameter symbol min typ max units notes data ( 1-wire) c in/out 800 pf 9 ac electrical characteristics regular speed v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 ? s write 1 low time t low1 1 15 ? s write 0 low time t low0 60 120 ? s read data valid t rdv exactly 15 ? s release time t release 0 15 45 ? s read data setup t su 1 ? s 5 recovery time t rec 1 ? s reset time high t rsth 480 ? s 4 reset time low t rstl 480 ? s presence detect high t pdh 15 60 ? s presence detect low t pdl 60 240 ? s delay to program t dp 5 ? s delay to verify t dv 5 ? s program pulse width t pp 480 ? s program voltage rise time t rp 0.5 5.0 ? s program voltage fall time t fp 0.5 5.0 ? s downloaded from: http:///
ds1986 27 of 28 ac electrical characteristics overdrive speed (v pup =2.8v to 6.0v; -40c to 70c) parameter symbol min typ max units notes time slot t slot 6 16 ? s write 1 low time t low1 1 2 ? s write 0 low time t low0 6 16 ? s read data valid t rdv exactly 2 ? s release time t release 0 1.5 4 ? s read data setup t su 1 ? s 5 recovery time t rec 1 ? s reset time high t rsth 48 ? s 4 reset time low t rstl 48 80 ? s presence detect high t pdh 2 6 ? s presence detect low t pdl 8 24 ? s notes: 1. all voltages are referenced to ground. 2. v pup = external pull-up voltage. 3. input load is to ground. 4. an additional reset or communication sequence ca nnot begin until the rese t high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 ? s of this falling edge. 6. v ih is a function of the external pull-up resistor and v pup . 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5 k ? pull-up to v cc and a maximum time slot of 120 ? s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k ? resistor is used to pull up the data line to v cc , 5 ? s after power has been applied the parasite capacitance will not affect normal communications. 10. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. downloaded from: http:///
ds1986 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. 28 of 28 revision history revision date description pages changed 071508 updated the f3 microcan and f5 microcan face brands with the latest per pcn h020201. 1 added the + sign to the part numbers in the ordering informatio n table, indicating lead(pb)-fre e/rohs-compliant packages. 1 8/09 removed the ul#913 bullet from the common i button features section. 1 downloaded from: http:///

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